1. Field of the Invention
The present invention relates generally to semiconductor fabrication. More specifically, the present invention relates to conditioning a working surface used in performing a chemical mechanical planarization (CMP) process.
2. Description of the Related Art
In the fabrication of semiconductor devices, planarization operations are often performed on a semiconductor wafer (“wafer”) to provide polishing, buffing, and cleaning effects. Typically, the wafer includes integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Patterned conductive layers are insulated from other conductive layers by a dielectric material. As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material increases. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to increased variations in a surface topography of the wafer. In other applications, metallization line patterns are formed into the dielectric material, and then metal planarization operations are performed to remove excess metallization.
The CMP process is one method for performing wafer planarization. In general, the CMP process involves holding and contacting a rotating wafer against a working surface of a moving polishing pad. CMP systems typically configure the polishing pad on a rotary table or a linear belt. Additionally, the CMP process can include the use of varying degrees of abrasives, chemistries, and fluids to maximize effective use of friction between the wafer and the working surface of the polishing pad. The abrasives, chemistries, and fluids are combined to form a slurry that is introduced and distributed over the working surface of the polishing pad. Cleaning and conditioning of the working surface of the polishing pad can also be performed during processing to control interface conditions that exist between the wafer and the working surface.
The working surface of the polishing pad can be either porous or non-porous and generally incorporates topographical variations. During the CMP process, the working surface can become saturated and clogged with slurry and CMP process residue, particularly in low-lying and/or porous regions. Saturation and clogging of the working surface can introduce undesirable effects on the interface conditions between the wafer and working surface. The undesirable effects can be especially detrimental where minor changes in the interface conditions pose significant problems with the CMP process results (e.g., processing wafers having small feature sizes (<90 nanometers), processing wafers having relatively fragile underlying materials (low-k materials), etc. . . ). Therefore, some CMP systems incorporate a conditioning operation to condition or roughen the working surface of the polishing pad. The conditioning operation serves to increase a quantity and quality of asperities present on the working surface while also serving to dislodge slurry and CMP process residue. The conditioning operation is generally performed by applying a conditioning substrate to the working surface of the polishing pad. Friction induced between the conditioning substrate and the working surface causes the conditioning to occur. It should be appreciated that the conditioning operation results are capable of influencing the associated CMP process results, e.g., wafer material removal rates and stability.
In view of the foregoing, there is a need for an apparatus and a method to effectively implement the conditioning operation. Furthermore, it is desirable to optimize an effectiveness and a longevity of the conditioning substrate used to perform the conditioning operation.